VLSI (CMOS & BICMOS)

 BiCMOS: Bipolar complementary metal-oxide-semiconductor

BiCMOS technology is a combination of Bipolar and CMOS technology. CMOS technology offers less power dissipation, smaller noise margins, and higher packing density. Bipolar technology, on the other hand, ensures high switching and I/O speed and good noise performance.It provides NMOS and PMOS technologies amalgamated with the advantages of having very low power consumption bipolar technology and high speed over CMOS technology.BiCMOS technology offers the advantages of Improved speed over CMOS, Lower power dissipation than Bipolar (simplifying packaging and board requirements), Flexible I/Os (TTL, CMOS, or ECL), High-performance analog, & Latchup immunity Compared to CMOS, BiCMOS’s reduced dependence on capacitive load and the multiple circuits and I/Os configurations possible greatly enhance design flexibility and can lead to reduced design cycle time.

CMOS:

Complementary Metal Oxide Semiconductor is termed CMOS.

CMOS Technology uses both PMOS and NMOS transistor

i)PMOS(Positive Metal Oxide Semiconductor)

ii)NMOS(Negative Metal Oxide Semiconductor)

Cmos circuits use a combination of PMOS and NMOS transistors to implement logic gates and other digital circuits found in computers, telecommunication equipment, and signal processing equipment.

CMOS has characteristics very close to that of an ideal logic family. An ideal logic family should dissipate no power, should have zero propagation delay, controlled rise and fall times, and have good noise immunity.

NMOS and PMOS transistors are not ideal switches. NMOS pass strong ‘0’ but a degraded or weak ‘1’ (pull no higher than VDD-Vtn); whereas PMOS pass strong ‘1’ but a degraded or weak ‘0’ (pull no lower than |Vtp|). Hence, NMOS is best for pull-down network, whereas PMOS are best for pull-up network.

Comments

Post a Comment

Popular posts from this blog

VLSI (CMOS LATCH UP)

Image
 LATCH UP IN CMOS: what is meant by latch-up? Generation of low impedance patch between the Vdd and GND in CMOS circuit. This makes a high amount of current driven from Vdd to GND by this the CMOS will be destroyed. SCR analogy to understand the latch-up: let us take four-layer SCR like below and apply Vdd at the anode and GND at the cathode. after you are given the Vdd and GND, if we give a trigger( small pulse) at the gate the SCR will Turn ON now current flows through it but there is no chance to turn it Off, This is called latch-up in SCR. The above scenario is the same in the transistor topology of SCR. LATCH UP IN BASIC CMOS INVERTER: By redrawing the Mos circuit using Transistors we get: We can observe that the circuit we just drawn is the same as the circuit of SCR using transistors. There are two conditions in which the LATCH-UP happens they are: 1. if  Vout > Vdd: in this case, the emitter of Q1 is high so as a result, the emitter-base junction gets forward biased...
Read more

VLSI (STATIC POWER CONSUMPTION IN CMOS)

Image
 STATIC POWER CONSUMPTION IN CMOS: The current that flows between the power rails when there is no switching activity i.e, there is no switching taking place from 0--->1 or 1---->0 at the input it is more like a steady-state. There is, unfortunately, a leakage current flowing through the reverse-biased diode junctions of the transistors, located between the source or drain and the substrate.  This contribution is, in general, very small and can be ignored. however this leakage current is increased by temperature. Their value increases with increasing junction temperature, and this occurs in an exponential fashion.
Read more