VLSI (LOGIC STYLE CLASSIFICATION)

 


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VLSI (PROPAGATION DELAY)

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 PROPAGATION DELAY: The time required for charging/discharging to change the output from logic 0 to logic 1 or vice versa is called propagation delay. propagation delay(Tpd) should be as low as possible to get fast switching speeds. CMOS is a single RC network and propagation delay of such circuit if excited by V step voltage is :                              tphl = ln(2) Reqn CL = 0.69 Req CL                              tplh = ln(2) Reqp CL = 0. 69 Req CL the total propagation delay is                                tp=(tphl+tplh)/2 = 0. 69(Reqn + Reqp)/2 propagation delay can be reduced in the following ways: Reduced CL : careful design of CMOS reduces diffusion and interconnection capacitances. Increase in W with cons...
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VLSI (NOISE MARGIN)

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 NOISE MARGIN: it is defined as up to what extent noise is allowed so that there is proper extraction of logic 1 and logic 0. NMh is the noise margin for logic high. NMl is the noise margin for logic low. this above noise margin explains that even if you connect the output of the circuit to another circuit at the input that much noise is allowed(NMh, NMl). the gap between Vih and 
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VLSI (MOSFET CAPACITANCES)

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 MOSFET CAPACITANCES: speed of the integrated circuit is limited by capacitance so that is why we should study this topic. here we will know the capacitances present in the MOSFET i.e., distributed capacitances( capacitance formed at lower frequency). MOS CAPACITANCES AT DIFFERENT REGIONS:
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