VLSI (LOGIC STYLE CLASSIFICATION)

 


Comments

Post a Comment

Popular posts from this blog

VLSI (CMOS & BICMOS)

Image
  BiCMOS : Bipolar complementary metal-oxide-semiconductor BiCMOS technology  is a combination of Bipolar and CMOS technology. CMOS technology offers less power dissipation, smaller noise margins, and higher packing density. Bipolar technology, on the other hand, ensures high switching and I/O speed and good noise performance . It provides NMOS and PMOS technologies amalgamated with the advantages of having very low power consumption bipolar technology and high speed over CMOS technology.BiCMOS technology offers the advantages of  Improved speed over CMOS, Lower power dissipation than Bipolar (simplifying packaging and board requirements), Flexible I/Os (TTL, CMOS, or ECL), High-performance analog, & Latchup immunity Compared to CMOS , BiCMOS’s reduced dependence on capacitive load and the multiple circuits and I/Os configurations possible greatly enhance design flexibility and can lead to reduced design cycle time. CMOS : Complementary Metal Oxide Semiconductor is te...
Read more

VLSI (MOSFET CAPACITANCES)

Image
 MOSFET CAPACITANCES: speed of the integrated circuit is limited by capacitance so that is why we should study this topic. here we will know the capacitances present in the MOSFET i.e., distributed capacitances( capacitance formed at lower frequency). MOS CAPACITANCES AT DIFFERENT REGIONS:
Read more

VLSI (PROPAGATION DELAY)

Image
 PROPAGATION DELAY: The time required for charging/discharging to change the output from logic 0 to logic 1 or vice versa is called propagation delay. propagation delay(Tpd) should be as low as possible to get fast switching speeds. CMOS is a single RC network and propagation delay of such circuit if excited by V step voltage is :                              tphl = ln(2) Reqn CL = 0.69 Req CL                              tplh = ln(2) Reqp CL = 0. 69 Req CL the total propagation delay is                                tp=(tphl+tplh)/2 = 0. 69(Reqn + Reqp)/2 propagation delay can be reduced in the following ways: Reduced CL : careful design of CMOS reduces diffusion and interconnection capacitances. Increase in W with cons...
Read more