VLSI (LOGIC STYLE CLASSIFICATION)

 


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VLSI (CMOS LATCH UP)

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 LATCH UP IN CMOS: what is meant by latch-up? Generation of low impedance patch between the Vdd and GND in CMOS circuit. This makes a high amount of current driven from Vdd to GND by this the CMOS will be destroyed. SCR analogy to understand the latch-up: let us take four-layer SCR like below and apply Vdd at the anode and GND at the cathode. after you are given the Vdd and GND, if we give a trigger( small pulse) at the gate the SCR will Turn ON now current flows through it but there is no chance to turn it Off, This is called latch-up in SCR. The above scenario is the same in the transistor topology of SCR. LATCH UP IN BASIC CMOS INVERTER: By redrawing the Mos circuit using Transistors we get: We can observe that the circuit we just drawn is the same as the circuit of SCR using transistors. There are two conditions in which the LATCH-UP happens they are: 1. if  Vout > Vdd: in this case, the emitter of Q1 is high so as a result, the emitter-base junction gets forward biased...
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VLSI (STATIC POWER CONSUMPTION IN CMOS)

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 STATIC POWER CONSUMPTION IN CMOS: The current that flows between the power rails when there is no switching activity i.e, there is no switching taking place from 0--->1 or 1---->0 at the input it is more like a steady-state. There is, unfortunately, a leakage current flowing through the reverse-biased diode junctions of the transistors, located between the source or drain and the substrate.  This contribution is, in general, very small and can be ignored. however this leakage current is increased by temperature. Their value increases with increasing junction temperature, and this occurs in an exponential fashion.
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