VLSI (LOGIC STYLE CLASSIFICATION)

 


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VLSI (PROPAGATION DELAY)

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 PROPAGATION DELAY: The time required for charging/discharging to change the output from logic 0 to logic 1 or vice versa is called propagation delay. propagation delay(Tpd) should be as low as possible to get fast switching speeds. CMOS is a single RC network and propagation delay of such circuit if excited by V step voltage is :                              tphl = ln(2) Reqn CL = 0.69 Req CL                              tplh = ln(2) Reqp CL = 0. 69 Req CL the total propagation delay is                                tp=(tphl+tplh)/2 = 0. 69(Reqn + Reqp)/2 propagation delay can be reduced in the following ways: Reduced CL : careful design of CMOS reduces diffusion and interconnection capacitances. Increase in W with cons...
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VLSI (CMOS LATCH UP)

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 LATCH UP IN CMOS: what is meant by latch-up? Generation of low impedance patch between the Vdd and GND in CMOS circuit. This makes a high amount of current driven from Vdd to GND by this the CMOS will be destroyed. SCR analogy to understand the latch-up: let us take four-layer SCR like below and apply Vdd at the anode and GND at the cathode. after you are given the Vdd and GND, if we give a trigger( small pulse) at the gate the SCR will Turn ON now current flows through it but there is no chance to turn it Off, This is called latch-up in SCR. The above scenario is the same in the transistor topology of SCR. LATCH UP IN BASIC CMOS INVERTER: By redrawing the Mos circuit using Transistors we get: We can observe that the circuit we just drawn is the same as the circuit of SCR using transistors. There are two conditions in which the LATCH-UP happens they are: 1. if  Vout > Vdd: in this case, the emitter of Q1 is high so as a result, the emitter-base junction gets forward biased...
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VLSI (NOISE MARGIN)

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 NOISE MARGIN: it is defined as up to what extent noise is allowed so that there is proper extraction of logic 1 and logic 0. NMh is the noise margin for logic high. NMl is the noise margin for logic low. this above noise margin explains that even if you connect the output of the circuit to another circuit at the input that much noise is allowed(NMh, NMl). the gap between Vih and 
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